diff -Ncwr utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S
*** utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-10-25 19:18:51.000000000 +0900
--- utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-10-25 19:30:33.000000000 +0900
***************
*** 80,86 ****
  
  Csym(knl_dispatch_to_schedtsk):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.l	#(Csym(knl_tmp_stack) + TMP_STACK_SZ), er7	// Set temporal stack
  
  	sub.w	r0, r0
  	inc.w	#1, r0				// r0 := 1
--- 80,86 ----
  
  Csym(knl_dispatch_to_schedtsk):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.w	#(Csym(knl_tmp_stack) + TMP_STACK_SZ), r7	// Set temporal stack
  
  	sub.w	r0, r0
  	inc.w	#1, r0				// r0 := 1
***************
*** 121,127 ****
  	mov.w	@er6, r1
  	mov.w	@Csym(CTXB_ssp), e1
  	add.w	e1, r1                          // er1 = &ctxtsk.ssp
! 	mov.l	er7, @er1                       // Save SSP to TCB
  
    l_dispatch0:
  	/* During interrupt enable CPSR.I=0 F=0 */
--- 121,127 ----
  	mov.w	@er6, r1
  	mov.w	@Csym(CTXB_ssp), e1
  	add.w	e1, r1                          // er1 = &ctxtsk.ssp
! 	mov.w	r7, @er1                       // Save SSP to TCB
  
    l_dispatch0:
  	/* During interrupt enable CPSR.I=0 F=0 */
***************
*** 148,154 ****
  	mov.w	r5, @er6			// ctxtsk = schedtsk
  	mov.w	@Csym(CTXB_ssp), r1
  	add.w	r5, r1
! 	mov.l	@er1, er7			// Restore SSP from TCB
  
  	sub.w	r1, r1
  	mov.w	r1, @Csym(knl_dispatch_disabled)	// Dispatch enable 
--- 148,154 ----
  	mov.w	r5, @er6			// ctxtsk = schedtsk
  	mov.w	@Csym(CTXB_ssp), r1
  	add.w	r5, r1
! 	mov.w	@er1, r7			// Restore SSP from TCB
  
  	sub.w	r1, r1
  	mov.w	r1, @Csym(knl_dispatch_disabled)	// Dispatch enable 
***************
*** 201,209 ****
  	mov.w	r5, r5
  	bne	l_no_change_sp		// multiple interrupt
  
! 	mov.l	er7, er2
! 	mov.l	#RI_INTSTACK, er7	// change to ISP
! 	mov.l	er2, @-er7		// SSP save
    l_no_change_sp:
  
  	shll.l	er0			// offset = dintno << 1
--- 201,209 ----
  	mov.w	r5, r5
  	bne	l_no_change_sp		// multiple interrupt
  
! 	mov.w	r7, r2
! 	mov.w	#RI_INTSTACK, r7	// change to ISP
! 	mov.w	r2, @-er7		// SSP save
    l_no_change_sp:
  
  	shll.l	er0			// offset = dintno << 1
***************
*** 216,223 ****
  	mov.w	r5, r5
  	bne	l_no_change_sp2		// multiple interrupt
  
! 	mov.l	@er7+, er2		// er2 = SSP
! 	mov.l	er2, er7
  l_no_change_sp2:
  
  	dec.w	#1, r6
--- 216,223 ----
  	mov.w	r5, r5
  	bne	l_no_change_sp2		// multiple interrupt
  
! 	mov.w	@er7+, r2		// r2 = SSP
! 	mov.w	r2, r7
  l_no_change_sp2:
  
  	dec.w	#1, r6
***************
*** 256,262 ****
  Csym(tk_ret_int_impl):
  	/* During interrupt disable SR.I=15 BL=1 RB=1 */
  #if USE_TRAP
! 	add.l	#4, er7		// Trash parts saved by 'trapa TRAP_RETINT'
  #endif
  
  	mov.w	@Csym(knl_int_nest), r0		// Is it a nesting interrupt?
--- 256,262 ----
  Csym(tk_ret_int_impl):
  	/* During interrupt disable SR.I=15 BL=1 RB=1 */
  #if USE_TRAP
! 	add.w	#4, r7		// Trash parts saved by 'trapa TRAP_RETINT'
  #endif
  
  	mov.w	@Csym(knl_int_nest), r0		// Is it a nesting interrupt?
***************
*** 396,411 ****
  #if CFN_MAX_SSYID > 0
  /*
   *	High Address	    +-------------------+
!  *			+34 | 5th arg(low)	|
!  *			+32 | 5th arg(high)	|
!  *			+30 | 4th arg(low)	|
!  *			+28 | 4th arg(high)	|
!  *			+26 | 3rd arg(low)	|
!  *			+24 | 3rd arg(high)	|
!  *			+22 | 2nd arg(low)	|
!  *			+20 | 2nd arg(high)	|
!  *			+18 | 1st arg(low)	|
!  *	pk_para(r1)=>	+16 | 1st arg(high)	|
   *			+14 | PC		| saved by trapa
   *			+12 | CCR:xxx		|
   *			+10 | R4		|
--- 396,413 ----
  #if CFN_MAX_SSYID > 0
  /*
   *	High Address	    +-------------------+
!  *			+38 | 5th arg(low)	|
!  *			+36 | 5th arg(high)	|
!  *			+34 | 4th arg(low)	|
!  *			+32 | 4th arg(high)	|
!  *			+30 | PC		| saved by I/F call
!  *			+28 | dummy		|
!  *			+26 | 2nd arg(low)	|
!  *			+24 | 2nd arg(high)	|
!  *			+22 | 1st arg(low)	|
!  *	pk_para(r1)=>	+20 | 1st arg(high)	|
!  *			+18 | 3rd arg(low)	|
!  *			+16 | 3rd arg(high)	|
   *			+14 | PC		| saved by trapa
   *			+12 | CCR:xxx		|
   *			+10 | R4		|
***************
*** 420,430 ****
--- 422,437 ----
   *	Function code is set in R0	 		
   */
  	/* Extended SVC */
+ 	mov.w	@(30, er7), r4		// save ret-address(I/F) to R4
+ 	mov.l	@(16, er7), er2		// arg3
+ 	mov.l	er2, @(28, er7)	
  	mov.w	r1, r2			// save R1 (pk_para) to R2
  	mov.w	r0, r1			// R1 = Function code
  	mov.w	r2, r0			// restore pk_para to R0
  	jsr	Csym(knl_svc_ientry)	// svc_ientry(pk_para, fncd)
  
+ 	mov.w	r4, @(30, er7)		// restore ret-address(I/F)
+ 
  	bra	l_retsvc
  #else
  	mov.l	#E_SYS, er0
***************
*** 463,471 ****
  	mov.w	r5, r5
  	bne	l_no_change_sp_timerhdr		// multiple interrupt
  
! 	mov.l	er7, er2
! 	mov.l	#RI_INTSTACK, er7	// change to ISP
! 	mov.l	er2, @-er7		// SSP save
    l_no_change_sp_timerhdr:
  
  	jsr	@Csym(knl_timer_handler)	// call timer_handler()
--- 470,478 ----
  	mov.w	r5, r5
  	bne	l_no_change_sp_timerhdr		// multiple interrupt
  
! 	mov.w	r7, r2
! 	mov.w	#RI_INTSTACK, r7	// change to ISP
! 	mov.w	r2, @-er7		// SSP save
    l_no_change_sp_timerhdr:
  
  	jsr	@Csym(knl_timer_handler)	// call timer_handler()
***************
*** 476,483 ****
  	mov.w	r5, r5
  	bne	l_no_change_sp2_timerhdr		// multiple interrupt
  
! 	mov.l	@er7+, er2		// ER2 = SSP
! 	mov.l	er2, er7
    l_no_change_sp2_timerhdr:
  
  	dec.w	#1, r6
--- 483,490 ----
  	mov.w	r5, r5
  	bne	l_no_change_sp2_timerhdr		// multiple interrupt
  
! 	mov.w	@er7+, r2		// R2 = SSP
! 	mov.w	r2, r7
    l_no_change_sp2_timerhdr:
  
  	dec.w	#1, r6
diff -Ncwr utkernel_source.prev/kernel/sysdepend/device/app_h8s2212/icrt0.S utkernel_source.curr/kernel/sysdepend/device/app_h8s2212/icrt0.S
*** utkernel_source.prev/kernel/sysdepend/device/app_h8s2212/icrt0.S	2007-09-29 15:03:24.000000000 +0900
--- utkernel_source.curr/kernel/sysdepend/device/app_h8s2212/icrt0.S	2007-10-25 19:19:37.000000000 +0900
***************
*** 35,41 ****
          .align     2
          .global    Csym(start)
  Csym(start):
! 	mov.l   #RI_INTSTACK, er7
  
  	ldc.b   #0xc0, ccr
  
--- 35,41 ----
          .align     2
          .global    Csym(start)
  Csym(start):
! 	mov.w   #RI_INTSTACK, r7
  
  	ldc.b   #0xc0, ccr