*** amd64errata.c.orig	Thu Jun 26 14:42:09 2008
--- amd64errata.c	Sat Feb 27 15:07:28 2010
***************
*** 51,56 ****
--- 51,58 ----
  #include <machine/cpufunc.h>
  #include <machine/specialreg.h>
  
+ #define	ERRATA_DEBUG
+ #define	ERRATA_VERBOSE
  
  typedef struct errata {
  	u_short		e_num;
***************
*** 64,69 ****
--- 66,72 ----
  typedef enum cpurev {
  	BH_E4, CH_CG, CH_D0, DH_CG, DH_D0, DH_E3, DH_E6, JH_E1,
  	JH_E6, SH_B0, SH_B3, SH_C0, SH_CG, SH_D0, SH_E4, SH_E5,
+ 	DR_BA, DR_B2, DR_B3,
  	OINK
  } cpurev_t;
  
***************
*** 78,83 ****
--- 81,87 ----
  	SH_CG, 0x0000f4a, SH_CG, 0x0000f5a, SH_CG, 0x0000f7a,
  	SH_D0, 0x0010f40, SH_D0, 0x0010f50, SH_D0, 0x0010f70,
  	SH_E4, 0x0020f51, SH_E4, 0x0020f71, SH_E5, 0x0020f42,
+ 	DR_BA, 0x0100f2a, DR_B2, 0x0100f22, DR_B3, 0x0100f23,
  	OINK
  };
  
***************
*** 117,122 ****
--- 121,134 ----
  	SH_D0, SH_D0, SH_D0, SH_E4, SH_E4, SH_E5, OINK
  };
  
+ static const uint8_t amd64_errata_set9[] = {
+ 	DR_BA, DR_B2, OINK
+ };
+ 
+ static const uint8_t amd64_errata_set10[] = {
+ 	DR_BA, DR_B2, DR_B3, OINK
+ };
+ 
  static int amd64_errata_setmsr(struct cpu_info *, errata_t *);
  static int amd64_errata_testmsr(struct cpu_info *, errata_t *);
  
***************
*** 178,184 ****
  		113, 0, MSR_BU_CFG, amd64_errata_set3,
  		amd64_errata_setmsr, BU_CFG_WBENHWSBDIS
  	},
- #ifdef MULTIPROCESSOR
  	/*
  	 * 69: Multiprocessor Coherency Problem with Hardware
  	 * Prefetch Mechanism
--- 190,195 ----
***************
*** 211,217 ****
  		107, 0, MSR_BU_CFG, amd64_errata_set2,
  		amd64_errata_testmsr, BU_CFG_THRL2IDXCMPDIS
  	},
- #if 0
  	/*
  	 * 122: TLB Flush Filter May Cause Coherency Problem in
  	 * Multiprocessor Systems
--- 222,227 ----
***************
*** 220,227 ****
  		122, 0, MSR_HWCR, amd64_errata_set4,
  		amd64_errata_setmsr, HWCR_FFDIS
  	},
! #endif
! #endif	/* MULTIPROCESSOR */
  };
  
  static int 
--- 230,270 ----
  		122, 0, MSR_HWCR, amd64_errata_set4,
  		amd64_errata_setmsr, HWCR_FFDIS
  	},
! 	/*
! 	 * 254: Internal Resource Livelock Involving Cached TLB Reload
! 	 */
! 	{
! 		254, 0, MSR_BU_CFG, amd64_errata_set9,
! 		amd64_errata_testmsr, BU_CFG_ERRATA_254
! 	},
! 	/*
! 	 * 261: Processor May Stall Entering Stop-Grant Due to Pending Data
! 	 * Cache Scrub
! 	 */
! 	{
! 		261, 0, MSR_DC_CFG, amd64_errata_set10,
! 		amd64_errata_testmsr, DC_CFG_ERRATA_261
! 	},
! 	/*
! 	 * 298: L2 Eviction May Occur During Processor Operation To Set
! 	 * Accessed or Dirty Bit
! 	 */
! 	{
! 		298, 0, MSR_HWCR, amd64_errata_set9,
! 		amd64_errata_testmsr, HWCR_TLBCACHEDIS
! 	},
! 	{
! 		298, 0, MSR_BU_CFG, amd64_errata_set9,
! 		amd64_errata_testmsr, BU_CFG_ERRATA_298
! 	},
! 	/*
! 	 * 309: Processor Core May Execute Incorrect Instructions on
! 	 * Concurrent L2 and Northbridge Response
! 	 */
! 	{
! 		309, 0, MSR_BU_CFG, amd64_errata_set9,
! 		amd64_errata_testmsr, BU_CFG_ERRATA_309
! 	},
  };
  
  static int