#define SystemControlBase	0xe01fc000
#define MEMMAP			(SystemControlBase + 0x0040)
#define PLLCON			(SystemControlBase + 0x0080)
#define PLLCFG			(SystemControlBase + 0x0084)
#define PLLSTAT			(SystemControlBase + 0x0088)
#define PLLFEED			(SystemControlBase + 0x008c)
#define PCONP			(SystemControlBase + 0x00c4)
#define APBDIV			(SystemControlBase + 0x0100)	// LPC21xx/22xx
#define CCLKCFG			(SystemControlBase + 0x0104)	// LPC23xx
#define USBCLKCFG		(SystemControlBase + 0x0108)	// LPC23xx
#define CLKSRCSEL		(SystemControlBase + 0x010c)	// LPC23xx
#define PCLKSEL0		(SystemControlBase + 0x01a8)	// LPC23xx
#define PCLKSEL1		(SystemControlBase + 0x01ac)	// LPC23xx

// board setup code ----------------------------------------------------------

	mov	r0, #0
	mov	r1, #1

memmap_init:	// remap vector area (boot loader -> user flash)
	ldr	r2, =MEMMAP
	str	r1, [r2]

pll_init:	// setup PLL
	ldr	r4, =PLLCON
	mov	r5, #0x55
	mov	r6, #0xaa

	ldr	r2, [r4, #0x08]		// PLLSTAT
	tst	r2, #(1 << 25)
					// PLL is connected: disconnect now
	strne	r1, [r4, #0x00]		// PLLCON=1 (PLL enable/disconnect)
	strne	r6, [r4, #0x0c]		//  PLLFEED=0xaa
	strne	r5, [r4, #0x0c]		//  PLLFEED=0x55

	str	r0, [r4, #0x00]		// PLLCON=0 (PLL disable/disconnect)
	str	r6, [r4, #0x0c]		//  PLLFEED=0xaa
	str	r5, [r4, #0x0c]		//  PLLFEED=0x55

	ldr	r2, =CLKSRCSEL		// clock source: internal RC-OSC, 4MHz
	str	r0, [r2]

	mov	r2, #((2 - 1) << 16)	// Fcco = (2 x M x Fin) / N
	orr	r2, r2, #(72 - 1)	//  288MHz = (2 x 72 x 4MHz) / 2
	str	r2, [r4, #0x04]		// PLLCFG
	str	r6, [r4, #0x0c]		//  PLLFEED=0xaa
	str	r5, [r4, #0x0c]		//  PLLFEED=0x55

	str	r1, [r4, #0x00]		// PLLCON=1 (PLL enable/disconnect)
	str	r6, [r4, #0x0c]		//  PLLFEED=0xaa
	str	r5, [r4, #0x0c]		//  PLLFEED=0x55

pll_wait:
	ldr	r2, [r4, #0x08]		// PLLSTAT
	tst	r2, #(1 << 26)
	beq	pll_wait		// wait for lock

	ldr	r2, =CCLKCFG		// CPU Clock: PLL clock / 4
	mov	r3, #(4 - 1)
	str	r3, [r2]

	mov	r3, #3
	str	r3, [r4, #0x00]		// PLLCON=3 (PLL enable/connect)
	str	r6, [r4, #0x0c]		//  PLLFEED=0xaa
	str	r5, [r4, #0x0c]		//  PLLFEED=0x55

pclk_init:	// setup PCLK
	ldr	r2, =PCLKSEL0		// PCLK=CCLK/4 (LPC23xx)
	str	r0, [r2, #0x00]		// PCLKSEL0
	str	r0, [r2, #0x04]		// PCLKSEL1