diff -Ncwr utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S
*** utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-09-29 15:03:23.000000000 +0900
--- utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-09-30 14:44:41.000000000 +0900
***************
*** 176,191 ****
  	stm.l	(er2-er3), @-er7	// er0-er1 are already saved
  	stm.l	(er4-er6), @-er7
  
! 	mov.l	@Csym(knl_taskindp), er6	// enter task independent mode
! 	inc.l	#1, er6
! 	mov.l	er6, @Csym(knl_taskindp)
! 
! 	mov.l	@Csym(knl_int_nest), er2	// interrupt nest count
! 	mov.l	er2, er5
! 	inc.l	#1, er2
! 	mov.l	er2, @Csym(knl_int_nest)
  
! 	mov.l	er5, er5
  	bne	l_no_change_sp		// multiple interrupt
  
  	mov.l	er7, er2
--- 176,191 ----
  	stm.l	(er2-er3), @-er7	// er0-er1 are already saved
  	stm.l	(er4-er6), @-er7
  
! 	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
! 	inc.w	#1, r6
! 	mov.w	r6, @Csym(knl_taskindp)
! 
! 	mov.w	@Csym(knl_int_nest), r2		// interrupt nest count
! 	mov.w	r2, r5
! 	inc.w	#1, r2
! 	mov.w	r2, @Csym(knl_int_nest)
  
! 	mov.w	r5, r5
  	bne	l_no_change_sp		// multiple interrupt
  
  	mov.l	er7, er2
***************
*** 193,214 ****
  	mov.l	er2, @-er7		// SSP save
    l_no_change_sp:
  
! 	shll.l	#2, er0			// offset = dintno << 2
! 	mov.l	@(Csym(knl_hll_inthdr), er0), er3	// call hll_inthdr[n](dintno)
  	jsr	@er3
  
  	orc.b	#CCR_I, ccr		// Interrupt disable
  
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.l	er5, er5
  	bne	l_no_change_sp2		// multiple interrupt
  
  	mov.l	@er7+, er2		// er2 = SSP
  	mov.l	er2, er7
  l_no_change_sp2:
  
! 	dec.l	#1, er6
! 	mov.l	er6, @Csym(knl_taskindp)
  
  	ldm.l	@er7+, (er4-er6)
  	ldm.l	@er7+, (er2-er3)
--- 193,214 ----
  	mov.l	er2, @-er7		// SSP save
    l_no_change_sp:
  
! 	shll.l	er0			// offset = dintno << 1
! 	mov.w	@(Csym(knl_hll_inthdr), er0), r3	// call hll_inthdr[n](dintno)
  	jsr	@er3
  
  	orc.b	#CCR_I, ccr		// Interrupt disable
  
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.w	r5, r5
  	bne	l_no_change_sp2		// multiple interrupt
  
  	mov.l	@er7+, er2		// er2 = SSP
  	mov.l	er2, er7
  l_no_change_sp2:
  
! 	dec.w	#1, r6
! 	mov.w	r6, @Csym(knl_taskindp)
  
  	ldm.l	@er7+, (er4-er6)
  	ldm.l	@er7+, (er2-er3)
***************
*** 243,263 ****
  	add.l	#4, er7		// Trash parts saved by 'trapa TRAP_RETINT'
  #endif
  
! 	mov.l	@Csym(knl_int_nest), er0	// Is it a nesting interrupt?
! 	dec.l	#1, er0
! 	mov.l	er0, @Csym(knl_int_nest)
  	bne	l_nodispatch
  
  	mov.w	@(2*4, er7), r0		// CCR when EIT occurs
  	and.b	#CCR_I, r0h		// Is it an exception during interrupt disable?
  	bne	l_nodispatch
  
! 	mov.l	@Csym(knl_dispatch_disabled), er0	// Is it during dispatch disable?
  	bne	l_nodispatch
  
! 	mov.l	@Csym(knl_ctxtsk), er0		// Is dispatch required?
! 	mov.l	@Csym(knl_schedtsk), er1
! 	cmp	er0, er1
  	beq	l_nodispatch
  
  	ldm.l	@er7+, (er0-er1)	// ER0, ER1 restore
--- 243,263 ----
  	add.l	#4, er7		// Trash parts saved by 'trapa TRAP_RETINT'
  #endif
  
! 	mov.w	@Csym(knl_int_nest), r0		// Is it a nesting interrupt?
! 	dec.w	#1, r0
! 	mov.w	r0, @Csym(knl_int_nest)
  	bne	l_nodispatch
  
  	mov.w	@(2*4, er7), r0		// CCR when EIT occurs
  	and.b	#CCR_I, r0h		// Is it an exception during interrupt disable?
  	bne	l_nodispatch
  
! 	mov.w	@Csym(knl_dispatch_disabled), r0	// Is it during dispatch disable?
  	bne	l_nodispatch
  
! 	mov.w	@Csym(knl_ctxtsk), r0		// Is dispatch required?
! 	mov.w	@Csym(knl_schedtsk), r1
! 	cmp	r0, r1
  	beq	l_nodispatch
  
  	ldm.l	@er7+, (er0-er1)	// ER0, ER1 restore
***************
*** 346,356 ****
    l_nocopy:
  
  	and.w	#0x0ff0, r0	// r0 = function No. << 4
! 	shlr.w	#2, r0		// r0 = function No. << 2
! 	mov.w	r0, r4
! 	extu.l	er4		// er4 = function No. * 4
  	mov.w	@(3*4 + 4, er5), r0	// restore first argument
! 	mov.l	@(_svctbl, er4), er4
  	jsr	@er4			// micro T-Kernel system call
  #else
  	bra	l_illegal_svc
--- 346,357 ----
    l_nocopy:
  
  	and.w	#0x0ff0, r0	// r0 = function No. << 4
! 	shlr.w	r0		// r0 = function No. << 3
! 	shlr.w	r0		// r0 = function No. << 2
! 	shlr.w	r0		// r0 = function No. << 1
! 	mov.w	r0, r4		// r4 = function No. * 2
  	mov.w	@(3*4 + 4, er5), r0	// restore first argument
! 	mov.w	@(_svctbl, er4), r4
  	jsr	@er4			// micro T-Kernel system call
  #else
  	bra	l_illegal_svc
***************
*** 402,417 ****
  	stm.l	(er0-er3), @-er7
  	stm.l	(er4-er6), @-er7
  
! 	mov.l	@Csym(knl_taskindp), er6	// enter task independent mode
! 	inc.l	#1, er6
! 	mov.l	er6, @Csym(knl_taskindp)
! 
! 	mov.l	@Csym(knl_int_nest), er2	// interrupt nest count
! 	mov.l	er2, er5
! 	inc.l	#1, er2
! 	mov.l	er2, @Csym(knl_int_nest)
  
! 	mov.l	er5, er5
  	bne	l_no_change_sp_timerhdr		// multiple interrupt
  
  	mov.l	er7, er2
--- 403,418 ----
  	stm.l	(er0-er3), @-er7
  	stm.l	(er4-er6), @-er7
  
! 	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
! 	inc.w	#1, r6
! 	mov.w	r6, @Csym(knl_taskindp)
! 
! 	mov.w	@Csym(knl_int_nest), r2		// interrupt nest count
! 	mov.w	r2, r5
! 	inc.w	#1, r2
! 	mov.w	r2, @Csym(knl_int_nest)
  
! 	mov.w	r5, r5
  	bne	l_no_change_sp_timerhdr		// multiple interrupt
  
  	mov.l	er7, er2
***************
*** 424,438 ****
  	orc.b	#CCR_I, ccr		// Interrupt disable
  
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.l	er5, er5
  	bne	l_no_change_sp2_timerhdr		// multiple interrupt
  
  	mov.l	@er7+, er2		// ER2 = SSP
  	mov.l	er2, er7
    l_no_change_sp2_timerhdr:
  
! 	dec.l	#1, er6
! 	mov.l	er6, @Csym(knl_taskindp)
  
  	ldm.l	@er7+, (er4-er6)
  	ldm.l	@er7+, (er2-er3)
--- 425,439 ----
  	orc.b	#CCR_I, ccr		// Interrupt disable
  
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	mov.w	r5, r5
  	bne	l_no_change_sp2_timerhdr		// multiple interrupt
  
  	mov.l	@er7+, er2		// ER2 = SSP
  	mov.l	er2, er7
    l_no_change_sp2_timerhdr:
  
! 	dec.w	#1, r6
! 	mov.w	r6, @Csym(knl_taskindp)
  
  	ldm.l	@er7+, (er4-er6)
  	ldm.l	@er7+, (er2-er3)