diff -Ncwr utkernel_source.prev/config/sysdepend/app_h8s2212/utk_config_depend.h utkernel_source.curr/config/sysdepend/app_h8s2212/utk_config_depend.h
*** utkernel_source.prev/config/sysdepend/app_h8s2212/utk_config_depend.h	2007-09-29 15:03:23.000000000 +0900
--- utkernel_source.curr/config/sysdepend/app_h8s2212/utk_config_depend.h	2007-10-13 15:57:20.000000000 +0900
***************
*** 32,53 ****
  /* SYSCONF */
  #define CFN_TIMER_PERIOD	250
  #define CFN_MAX_TSKID		2
! #define CFN_MAX_SEMID		2
! #define CFN_MAX_FLGID		2
! #define CFN_MAX_MBXID		2
! #define CFN_MAX_MTXID		2
! #define CFN_MAX_MBFID		2
! #define CFN_MAX_PORID		2
! #define CFN_MAX_MPLID		2
! #define CFN_MAX_MPFID		2
! #define CFN_MAX_CYCID		2
! #define CFN_MAX_ALMID		2
! #define CFN_MAX_SSYID		2
! #define CFN_MAX_SSYPRI		2
! 
! #define CFN_MAX_REGDEV		(2)
! #define CFN_MAX_OPNDEV		(2)
! #define CFN_MAX_REQDEV		(2)
  #define CFN_DEVT_MBFSZ0		(-1)
  #define CFN_DEVT_MBFSZ1		(-1)
  
--- 32,53 ----
  /* SYSCONF */
  #define CFN_TIMER_PERIOD	250
  #define CFN_MAX_TSKID		2
! #define CFN_MAX_SEMID		1
! #define CFN_MAX_FLGID		1
! #define CFN_MAX_MBXID		1
! #define CFN_MAX_MTXID		0
! #define CFN_MAX_MBFID		0
! #define CFN_MAX_PORID		0
! #define CFN_MAX_MPLID		0
! #define CFN_MAX_MPFID		0
! #define CFN_MAX_CYCID		0
! #define CFN_MAX_ALMID		0
! #define CFN_MAX_SSYID		0
! #define CFN_MAX_SSYPRI		0
! 
! #define CFN_MAX_REGDEV		(0)
! #define CFN_MAX_OPNDEV		(0)
! #define CFN_MAX_REQDEV		(0)
  #define CFN_DEVT_MBFSZ0		(-1)
  #define CFN_DEVT_MBFSZ1		(-1)
  
diff -Ncwr utkernel_source.prev/include/sys/svc/tdsvctbl.h utkernel_source.curr/include/sys/svc/tdsvctbl.h
*** utkernel_source.prev/include/sys/svc/tdsvctbl.h	2007-03-12 20:25:51.000000000 +0900
--- utkernel_source.curr/include/sys/svc/tdsvctbl.h	2007-10-13 15:58:08.000000000 +0900
***************
*** 6,12 ****
  
  #include <machine.h>
  
! #define _TDSC_ENTRY(name)	.long	Csym(name##_impl)
  
  #define N_TDFN	46
  
--- 6,12 ----
  
  #include <machine.h>
  
! #define _TDSC_ENTRY(name)	.word	Csym(name##_impl)
  
  #define N_TDFN	46
  
diff -Ncwr utkernel_source.prev/include/sys/svc/tksvctbl.h utkernel_source.curr/include/sys/svc/tksvctbl.h
*** utkernel_source.prev/include/sys/svc/tksvctbl.h	2007-03-12 20:25:51.000000000 +0900
--- utkernel_source.curr/include/sys/svc/tksvctbl.h	2007-10-13 15:58:14.000000000 +0900
***************
*** 6,12 ****
  
  #include <machine.h>
  
! #define _SVC_ENTRY(name)	.long	Csym(name##_impl)
  
  #define N_TFN	99
  
--- 6,12 ----
  
  #include <machine.h>
  
! #define _SVC_ENTRY(name)	.word	Csym(name##_impl)
  
  #define N_TFN	99
  
diff -Ncwr utkernel_source.prev/include/tk/sysdepend/app_h8s2212/asm_depend.h utkernel_source.curr/include/tk/sysdepend/app_h8s2212/asm_depend.h
*** utkernel_source.prev/include/tk/sysdepend/app_h8s2212/asm_depend.h	2007-09-29 15:03:23.000000000 +0900
--- utkernel_source.curr/include/tk/sysdepend/app_h8s2212/asm_depend.h	2007-10-13 16:00:42.000000000 +0900
***************
*** 27,33 ****
   .macro	INT_ENTRY vecno
  	.global knl_inthdr_entry\vecno
  knl_inthdr_entry\vecno:
! 	stm.l	(er0-er1), @-er7	// ER0, ER1 save
  
  	sub.l	er0, er0
  	mov.b	#\vecno, r0l
--- 27,34 ----
   .macro	INT_ENTRY vecno
  	.global knl_inthdr_entry\vecno
  knl_inthdr_entry\vecno:
! 	push.l	er0
! 	push.l	er1
  
  	sub.l	er0, er0
  	mov.b	#\vecno, r0l
diff -Ncwr utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S
*** utkernel_source.prev/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-10-11 18:14:57.000000000 +0900
--- utkernel_source.curr/kernel/sysdepend/cpu/h8s2212/cpu_support.S	2007-10-13 16:11:18.000000000 +0900
***************
*** 109,116 ****
  	mov.w	r0, @Csym(knl_dispatch_disabled)	// Dispatch disable
  	andc	#CCR_EI_MASK, ccr		// Interrupt enable
  
! 	stm.l	(er0-er3), @-er7		// Context save
! 	stm.l	(er4-er6), @-er7
  
  	mov.w	#Csym(knl_ctxtsk), r6           // r6 := &ctxtsk
  	mov.w	@er6, r1
--- 109,121 ----
  	mov.w	r0, @Csym(knl_dispatch_disabled)	// Dispatch disable
  	andc	#CCR_EI_MASK, ccr		// Interrupt enable
  
! 	push.l	er0				// Context save
! 	push.l	er1
! 	push.l	er2
! 	push.l	er3
! 	push.l	er4
! 	push.l	er5
! 	push.l	er6
  
  	mov.w	#Csym(knl_ctxtsk), r6           // r6 := &ctxtsk
  	mov.w	@er6, r1
***************
*** 148,155 ****
  	sub.w	r1, r1
  	mov.w	r1, @Csym(knl_dispatch_disabled)	// Dispatch enable 
  
! 	ldm.l	@er7+, (er4-er6)		// Context restore
! 	ldm.l	@er7+, (er0-er3)
  
  	rte
  
--- 153,165 ----
  	sub.w	r1, r1
  	mov.w	r1, @Csym(knl_dispatch_disabled)	// Dispatch enable 
  
! 	pop.l	er6				// Context restore
! 	pop.l	er5
! 	pop.l	er4
! 	pop.l	er3
! 	pop.l	er2
! 	pop.l	er1
! 	pop.l	er0
  
  	rte
  
***************
*** 173,180 ****
  	.globl	Csym(knl_inthdr_startup)
  Csym(knl_inthdr_startup):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	stm.l	(er2-er3), @-er7	// er0-er1 are already saved
! 	stm.l	(er4-er6), @-er7
  
  	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
  	inc.w	#1, r6
--- 183,193 ----
  	.globl	Csym(knl_inthdr_startup)
  Csym(knl_inthdr_startup):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	push.l	er2			// er0-er1 are already saved
! 	push.l	er3
! 	push.l	er4
! 	push.l	er5
! 	push.l	er6
  
  	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
  	inc.w	#1, r6
***************
*** 210,217 ****
  	dec.w	#1, r6
  	mov.w	r6, @Csym(knl_taskindp)
  
! 	ldm.l	@er7+, (er4-er6)
! 	ldm.l	@er7+, (er2-er3)
  
  #if USE_TRAP
  	trapa	#TRAP_RETINT		// tk_ret_int()
--- 223,233 ----
  	dec.w	#1, r6
  	mov.w	r6, @Csym(knl_taskindp)
  
! 	pop.l	er6
! 	pop.l	er5
! 	pop.l	er4
! 	pop.l	er3
! 	pop.l	er2
  
  #if USE_TRAP
  	trapa	#TRAP_RETINT		// tk_ret_int()
***************
*** 260,270 ****
  	cmp	r0, r1
  	beq	l_nodispatch
  
! 	ldm.l	@er7+, (er0-er1)	// ER0, ER1 restore
  	jmp	_ret_int_dispatch	// To dispatch processing
  
    l_nodispatch:				// Dispatch not required
! 	ldm.l	@er7+, (er0-er1)	// ER0, ER1 restore
  	rte
  
  
--- 276,288 ----
  	cmp	r0, r1
  	beq	l_nodispatch
  
! 	pop.l	er1			// ER0, ER1 restore
! 	pop.l	er0
  	jmp	_ret_int_dispatch	// To dispatch processing
  
    l_nodispatch:				// Dispatch not required
! 	pop.l	er1			// ER0, ER1 restore
! 	pop.l	er0
  	rte
  
  
***************
*** 288,294 ****
  	.text
  	.balign	2
  _svctbl:
! 	.long	Csym(knl_no_support)
  #define	tk_ret_int_impl	knl_no_support
  #include <sys/svc/tksvctbl.h>
  #undef	tk_ret_int_impl
--- 306,312 ----
  	.text
  	.balign	2
  _svctbl:
! 	.word	Csym(knl_no_support)
  #define	tk_ret_int_impl	knl_no_support
  #include <sys/svc/tksvctbl.h>
  #undef	tk_ret_int_impl
***************
*** 316,324 ****
  	.globl	Csym(knl_call_entry)
  Csym(knl_call_entry):
  
! 	stm.l	(er4-er6), @-er7	// er4, er6 = working register
! 					// er6 is used for pass fncd
! 					//   between hook_enter and hook_leave
  	mov.l	er7, er5		// er5 = frame pointer
  
  #if USE_TRAP
--- 334,343 ----
  	.globl	Csym(knl_call_entry)
  Csym(knl_call_entry):
  
! 	push.l	er4			// er4, er6 = working register
! 	push.l	er5			// er6 is used for pass fncd
! 	push.l	er6			//   between hook_enter and hook_leave
! 
  	mov.l	er7, er5		// er5 = frame pointer
  
  #if USE_TRAP
***************
*** 362,368 ****
  	orc	#CCR_I, ccr
  
  	mov.l	er5, er7
! 	ldm.l	@er7+, (er4-er6)
  	rte
  
    l_illegal_svc:
--- 381,389 ----
  	orc	#CCR_I, ccr
  
  	mov.l	er5, er7
! 	pop.l	er6
! 	pop.l	er5
! 	pop.l	er4
  	rte
  
    l_illegal_svc:
***************
*** 400,407 ****
  	.globl	Csym(knl_timer_handler_startup)
  Csym(knl_timer_handler_startup):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	stm.l	(er0-er3), @-er7
! 	stm.l	(er4-er6), @-er7
  
  	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
  	inc.w	#1, r6
--- 421,433 ----
  	.globl	Csym(knl_timer_handler_startup)
  Csym(knl_timer_handler_startup):
  	/* During interrupt disable SR.I=15 BL=0 RB=0 */
! 	push.l	er0
! 	push.l	er1
! 	push.l	er2
! 	push.l	er3
! 	push.l	er4
! 	push.l	er5
! 	push.l	er6
  
  	mov.w	@Csym(knl_taskindp), r6		// enter task independent mode
  	inc.w	#1, r6
***************
*** 435,442 ****
  	dec.w	#1, r6
  	mov.w	r6, @Csym(knl_taskindp)
  
! 	ldm.l	@er7+, (er4-er6)
! 	ldm.l	@er7+, (er2-er3)
  
  #if USE_TRAP
  	trapa	#TRAP_RETINT		// tk_ret_int()
--- 461,471 ----
  	dec.w	#1, r6
  	mov.w	r6, @Csym(knl_taskindp)
  
! 	pop.l	er6
! 	pop.l	er5
! 	pop.l	er4
! 	pop.l	er3
! 	pop.l	er2
  
  #if USE_TRAP
  	trapa	#TRAP_RETINT		// tk_ret_int()
diff -Ncwr utkernel_source.prev/lib/libtm/src/sysdepend/app_h8s2212/sio.c utkernel_source.curr/lib/libtm/src/sysdepend/app_h8s2212/sio.c
*** utkernel_source.prev/lib/libtm/src/sysdepend/app_h8s2212/sio.c	2007-03-12 20:26:25.000000000 +0900
--- utkernel_source.curr/lib/libtm/src/sysdepend/app_h8s2212/sio.c	2007-10-13 19:44:38.000000000 +0900
***************
*** 14,54 ****
  
  #include <basic.h>
  
! #define MSTP_CRB	(0x00fffde8UL + 1UL)
! #define PB_DR	(0x00fffe3aUL + 0xd0UL)
! #define SCI2_SMR	(0x00ffff88UL)
! #define SCI2_BRR	(0x00ffff89UL)
! #define SCI2_SCR	(0x00ffff8aUL)
! #define SCI2_TDR	(0x00ffff8bUL)
! #define SCI2_SSR	(0x00ffff8cUL)
! #define SCI2_RDR	(0x00ffff8dUL)
! #define SCI2_SCMR	(0x00ffff8eUL)
  
  
! #define CPUCLK		(4000000UL)				/* CPU clock : 4MHz */
  #define SYSCLK		(CPUCLK)				/* System clock (Hz) */
! #define RS_BAUD_RATE	(9600)				/* 9.6kbps */
  
  void Sci2AsyncMode( void );
  char Sci2AsyncTx(unsigned char Data);
  char Sci2AsyncRx(unsigned char *pData);
  
- 
- 
  int sio_send_frame(const unsigned char* buf, int size)
  {
  	int i;
  
- 	*((unsigned char*)MSTP_CRB) &= (unsigned char)~(1U << 5);
- 	*((unsigned char*)PB_DR) &= ~(1UL << 0);
  	Sci2AsyncMode();
! 	for(i = 0; i < size; i++) {
! 		Sci2AsyncTx(buf[i]);
! 	}
! 	*((unsigned char*)PB_DR) |= (1UL << 0);
! 	*((unsigned char*)SCI2_SCR) &= ~(1UL << 5);
! 	*((unsigned char*)SCI2_SCR) &= ~(1UL << 4);
! 	*((unsigned char*)MSTP_CRB) |= (1U << 5);
  
  	return i;
  }
--- 14,59 ----
  
  #include <basic.h>
  
! #define	PMR1		((_UB *)0xffe0)
! #define	TXD		(1 << 1)
  
+ #define	MSTCR1		((_UB *)0xfff9)
+ #define	MSTS3		(1 << 5)
  
! #define	SMR		((_UB *)0xffa8)
! #define	BRR		((_UB *)0xffa9)
! #define	SCR		((_UB *)0xffaa)
! #define	TDR		((_UB *)0xffab)
! #define	SSR		((_UB *)0xffac)
! #define	RDR		((_UB *)0xffad)
! 
! /* SSR */
! #define	TDRE		(1 << 7)
! #define	RDRF		(1 << 6)
! #define	OER		(1 << 5)
! #define	FER		(1 << 4)
! #define	PER		(1 << 3)
! #define	TEND		(1 << 2)
! 
! /* SCR */
! #define	TE		(1 << 5)
! #define	RE		(1 << 4)
! 
! #define CPUCLK		(16000000UL)			/* CPU clock : 16MHz */
  #define SYSCLK		(CPUCLK)			/* System clock (Hz) */
! #define	UARTCLK		(SYSCLK / 4)			/* UART clock */
! #define RS_BAUD_RATE	(9600UL)			/* 9.6kbps */
  
  void Sci2AsyncMode( void );
  char Sci2AsyncTx(unsigned char Data);
  char Sci2AsyncRx(unsigned char *pData);
  
  int sio_send_frame(const unsigned char* buf, int size)
  {
  	int i;
  
  	Sci2AsyncMode();
! 	for(i = 0; i < size; i++) Sci2AsyncTx(buf[i]);
  
  	return i;
  }
***************
*** 57,128 ****
  {
  	int i;
  
- 	*((unsigned char*)MSTP_CRB) &= (unsigned char)~(1U << 5);
- 	*((unsigned char*)PB_DR) &= ~(1UL << 0);
  	Sci2AsyncMode();
! 	for(i = 0; i < size; i++) {
! 		while(Sci2AsyncRx(&buf[i]) != 0) {
! 			;
! 		}
! 	}
! 	*((unsigned char*)PB_DR) |= (1UL << 0);
! 	*((unsigned char*)SCI2_SCR) &= ~(1UL << 5);
! 	*((unsigned char*)SCI2_SCR) &= ~(1UL << 4);
! 	*((unsigned char*)MSTP_CRB) |= (1U << 5);
  
  	return i;
  }
  
- void sio_nop(void) {
- 	Asm("nop\n\tnop\n\tnop\n\tnop");
- }
- 
  void Sci2AsyncMode( void )
  {
- 	unsigned char Brr;
  	unsigned long dly;
  
! 	*((unsigned char*)SCI2_SCR) = 0x00;			/* TE = 0 RE = 0 */
! 	*((unsigned char*)SCI2_SCMR) = 0x00;		/* LSB first */
! 	*((unsigned char*)SCI2_SMR) = 0x00;			/* Data8 Stop1 */
! 	Brr = (unsigned char)((1000000 / 64 * 2) / RS_BAUD_RATE * (CPUCLK / 1000 / 1000) +.5);
! 	*((unsigned char*)SCI2_BRR) = Brr;
  
! 	dly = SYSCLK / RS_BAUD_RATE;
! 	while ((dly--) != 0){ sio_nop(); }
  
! 	*((unsigned char*)SCI2_SCR) |= 0x30;		/* TE = 1 RE = 1 */
  }
  
  char Sci2AsyncTx(unsigned char Data)
  {
! 	while ((*((unsigned char*)SCI2_SSR) & (1U << 7)) == 0){};
! 	*((unsigned char*)SCI2_TDR) = Data;
! 	*((unsigned char*)SCI2_SSR) &= ~(1U << 7);
! 	while ((*((unsigned char*)SCI2_SSR) & (1U << 2)) == 0){};
! 	*((unsigned char*)SCI2_SSR) &= ~(1U << 2);
  
  	return 1;
  }
  
  char Sci2AsyncRx(unsigned char *pData)
  {
! 	if ((*((unsigned char*)SCI2_SSR) & (1U << 4)) != 0){
! 		*((unsigned char*)SCI2_SSR) &= ~(1U << 4);
  		return 1;
  	}
! 	if ((*((unsigned char*)SCI2_SSR) & (1U << 3)) != 0){
! 		*((unsigned char*)SCI2_SSR) &= ~(1U << 3);
  		return 2;
  	}
! 	if ((*((unsigned char*)SCI2_SSR) & (1U << 5)) != 0){
! 		*((unsigned char*)SCI2_SSR) &= ~(1U << 5);
  		return 3;
  	}
! 
! 	if ((*((unsigned char*)SCI2_SSR) & (1U << 6)) != 0){
! 		*pData = *((unsigned char*)SCI2_RDR);
! 		*((unsigned char*)SCI2_SSR) &= ~(1U << 6);
  		return 0;
  	}
  
--- 62,118 ----
  {
  	int i;
  
  	Sci2AsyncMode();
! 	for(i = 0; i < size; i++) while(Sci2AsyncRx(&buf[i]));
  
  	return i;
  }
  
  void Sci2AsyncMode( void )
  {
  	unsigned long dly;
  
! 	*MSTCR1 &= ~MSTS3;			// SCI3 power-up
! 	*PMR1 |= TXD;				// P22 -> TXD pin
! 
! 	*SCR = 0x00;				// TE=0, RE=0
! 	*SMR = 0x01;				// 8N1, system clock / 4
  
! 	*BRR = (UARTCLK + 64 * RS_BAUD_RATE) / (128 * RS_BAUD_RATE) - 1;
  
! 	dly = SYSCLK / (2 * RS_BAUD_RATE);
! 	while (dly--){ Asm("nop"); }
! 
! 	*SCR = TE | RE;
  }
  
  char Sci2AsyncTx(unsigned char Data)
  {
! 	while (!(*SSR & TDRE));
! 	*TDR = Data;
! 	while (!(*SSR & TEND));
  
  	return 1;
  }
  
  char Sci2AsyncRx(unsigned char *pData)
  {
! 	char	ssr = *SSR;
! 
! 	if (ssr & FER) {
! 		*SSR &= ~FER;
  		return 1;
  	}
! 	if (ssr & PER) {
! 		*SSR &= ~PER;
  		return 2;
  	}
! 	if (ssr & OER) {
! 		*SSR &= ~OER;
  		return 3;
  	}
! 	if (ssr & RDRF) {
! 		*pData = *RDR;
  		return 0;
  	}