diff -Ncwr h8mon.orig/h8mon.S h8mon.coff/h8mon.S
*** h8mon.orig/h8mon.S	2004-03-08 15:50:27.000000000 +0900
--- h8mon.coff/h8mon.S	2007-11-26 22:53:59.000000000 +0900
***************
*** 88,94 ****
  		beq		Main2
  		jsr		@er0
  Main2:
! 		andc.b		#~CCR_INTERRUPT, ccr	/* enable interrupt on CCR */
  
  #ifdef MULTIPLE_CONSOLE
  
--- 88,94 ----
  		beq		Main2
  		jsr		@er0
  Main2:
! 		andc.b		#(~CCR_INTERRUPT):8, ccr	/* enable interrupt on CCR */
  
  #ifdef MULTIPLE_CONSOLE
  
***************
*** 1445,1451 ****
  		orc.b		#CCR_INTERRUPT, ccr		/* disable interrupt on CCR */
  		mov.l		#_MonitorVector, er1
  		mov.l		er1, @CurrentVector
! 		andc.b		#~CCR_INTERRUPT, ccr		/* enable interrupt on CCR */
  		pop.l		er4
  		pop.l		er5
  		rts
--- 1445,1451 ----
  		orc.b		#CCR_INTERRUPT, ccr		/* disable interrupt on CCR */
  		mov.l		#_MonitorVector, er1
  		mov.l		er1, @CurrentVector
! 		andc.b		#(~CCR_INTERRUPT):8, ccr		/* enable interrupt on CCR */
  		pop.l		er4
  		pop.l		er5
  		rts
diff -Ncwr h8mon.orig/serial.S h8mon.coff/serial.S
*** h8mon.orig/serial.S	2004-02-21 11:40:48.000000000 +0900
--- h8mon.coff/serial.S	2007-11-26 22:53:13.000000000 +0900
***************
*** 170,176 ****
  		mov.b		@(SCITXBuffCount, er2), r0l
  		inc.b		r0l
  		mov.b		r0l, @(SCITXBuffCount, er2)
! 		andc.b		#~CCR_INTERRUPT, ccr		/* enable interrupt on CCR */
  
  		mov.b		@(SCITXFlowCntrl, er2), r0l
  		bne		SendChar3
--- 170,176 ----
  		mov.b		@(SCITXBuffCount, er2), r0l
  		inc.b		r0l
  		mov.b		r0l, @(SCITXBuffCount, er2)
! 		andc.b		#(~CCR_INTERRUPT):8, ccr		/* enable interrupt on CCR */
  
  		mov.b		@(SCITXFlowCntrl, er2), r0l
  		bne		SendChar3
***************
*** 301,307 ****
  		shll.l		er1
  		mov.b		r3h, @(IOREG_SCI_BASE + IOREG_TDR_OFFSET, er1)
  		mov.b		@(IOREG_SCI_BASE + IOREG_SSR_OFFSET, er1), r0l
! 		and.b		#~SSR_TDRE, r0l
  		mov.b		r0l, @(IOREG_SCI_BASE + IOREG_SSR_OFFSET, er1)
  
  		sub.b		r3h, r3h
--- 301,307 ----
  		shll.l		er1
  		mov.b		r3h, @(IOREG_SCI_BASE + IOREG_TDR_OFFSET, er1)
  		mov.b		@(IOREG_SCI_BASE + IOREG_SSR_OFFSET, er1), r0l
! 		and.b		#(~SSR_TDRE):8, r0l
  		mov.b		r0l, @(IOREG_SCI_BASE + IOREG_SSR_OFFSET, er1)
  
  		sub.b		r3h, r3h
***************
*** 314,320 ****
  		beq		ComInterTX4
  ComInterTX3:
  		mov.b		@(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1), r0h
! 		and.b		#~SCR_TIE, r0h
  		mov.b		r0h, @(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1)
  ComInterTX4:
  		pop.l		er2
--- 314,320 ----
  		beq		ComInterTX4
  ComInterTX3:
  		mov.b		@(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1), r0h
! 		and.b		#(~SCR_TIE):8, r0h
  		mov.b		r0h, @(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1)
  ComInterTX4:
  		pop.l		er2
***************
*** 459,465 ****
  		mov.b		@(SCIRXBuffCount, er2), r0l
  		dec.b		r0l
  		mov.b		r0l, @(SCIRXBuffCount, er2)
! 		andc.b		#~CCR_INTERRUPT, ccr		/* enable interrupt on CCR */
  
  		cmp.b		#SCI_LOW_WMARK, r0l		/* check low water mark */
  		bhs		ReciveChar2
--- 459,465 ----
  		mov.b		@(SCIRXBuffCount, er2), r0l
  		dec.b		r0l
  		mov.b		r0l, @(SCIRXBuffCount, er2)
! 		andc.b		#(~CCR_INTERRUPT):8, ccr		/* enable interrupt on CCR */
  
  		cmp.b		#SCI_LOW_WMARK, r0l		/* check low water mark */
  		bhs		ReciveChar2
***************
*** 478,484 ****
  		mov.b		@(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1), r0h
  		or.b		#SCR_TIE, r0h
  		mov.b		r0h, @(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1)
! 		andc.b		#~CCR_INTERRUPT, ccr		/* enable interrupt on CCR */
  ReciveChar2:
  		shll.l		er2
  		shll.l		er2
--- 478,484 ----
  		mov.b		@(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1), r0h
  		or.b		#SCR_TIE, r0h
  		mov.b		r0h, @(IOREG_SCI_BASE + IOREG_SCR_OFFSET, er1)
! 		andc.b		#(~CCR_INTERRUPT):8, ccr		/* enable interrupt on CCR */
  ReciveChar2:
  		shll.l		er2
  		shll.l		er2