Index: arch/arm64/conf/RAMDISK =================================================================== RCS file: /cvs/src/sys/arch/arm64/conf/RAMDISK,v retrieving revision 1.161 diff -u -p -u -p -r1.161 RAMDISK --- arch/arm64/conf/RAMDISK 22 Nov 2021 20:25:50 -0000 1.161 +++ arch/arm64/conf/RAMDISK 4 Dec 2021 21:42:08 -0000 @@ -230,7 +230,7 @@ sximmc* at fdt? # SD/MMC card controll sdmmc* at sximmc? # SD/MMC bus sxisid* at fdt? early 1 sxisyscon* at fdt? early 1 # System controller -sxitwi* at fdt? # I2C controller +sxitwi* at fdt? early 1 # I2C controller iic* at sxitwi? # I2C bus dwxe* at fdt? @@ -328,6 +328,7 @@ uk* at scsibus? # I2C devices abcrtc* at iic? # Abracon x80x RTC +axppmic* at iic? # AXP80x PMIC dsxrtc* at iic? # DS3231 RTC fusbtc* at iic? # USB Type-C controller islrtc* at iic? # ISL1208 RTC Index: dev/fdt/com_fdt.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/com_fdt.c,v retrieving revision 1.6 diff -u -p -u -p -r1.6 com_fdt.c --- dev/fdt/com_fdt.c 24 Oct 2021 17:52:26 -0000 1.6 +++ dev/fdt/com_fdt.c 4 Dec 2021 21:42:11 -0000 @@ -33,8 +33,6 @@ #include #include -#define com_usr 31 /* Synopsys DesignWare UART */ - int com_fdt_match(struct device *, void *, void *); void com_fdt_attach(struct device *, struct device *, void *); int com_fdt_intr_designware(void *); @@ -144,8 +142,10 @@ com_fdt_attach(struct device *parent, st sc->sc_reg_shift = OF_getpropint(faa->fa_node, "reg-shift", shift); if (OF_is_compatible(faa->fa_node, "snps,dw-apb-uart") || - OF_is_compatible(faa->fa_node, "marvell,armada-38x-uart")) + OF_is_compatible(faa->fa_node, "marvell,armada-38x-uart")) { + sc->sc_uarttype = COM_UART_DW_APB; intr = com_fdt_intr_designware; + } if (OF_is_compatible(faa->fa_node, "ti,omap3-uart") || OF_is_compatible(faa->fa_node, "ti,omap4-uart")) Index: dev/fdt/if_dwxe.c =================================================================== RCS file: /cvs/src/sys/dev/fdt/if_dwxe.c,v retrieving revision 1.19 diff -u -p -u -p -r1.19 if_dwxe.c --- dev/fdt/if_dwxe.c 24 Oct 2021 17:52:26 -0000 1.19 +++ dev/fdt/if_dwxe.c 4 Dec 2021 21:42:11 -0000 @@ -41,6 +41,7 @@ #include #include +#include #include #include #include @@ -348,6 +349,7 @@ void dwxe_iff(struct dwxe_softc *); int dwxe_encap(struct dwxe_softc *, struct mbuf *, int *); void dwxe_reset(struct dwxe_softc *); +void dwxe_reset_phy(void); void dwxe_stop_dma(struct dwxe_softc *); struct dwxe_dmamem * @@ -367,6 +369,54 @@ dwxe_match(struct device *parent, void * } void +dwxe_reset_phy(void) +{ + int node, t1, t2; + uint32_t phandle, port, pin, flags; + uint32_t gpio[4]; + + node = OF_finddevice("/"); + if (!node) + return; + + /* + * There is no binding definiton about the GPIO that is used for + * resetting external PHY. But some boards have GPIO connected to + * PHY's reset and need to assert at dwxe_attach(). + * This is workaround. + */ + if (OF_is_compatible(node, "xunlong,orangepi-one-plus")) { + /* PD14, active-low */ + port = 3; + pin = 14; + flags = GPIO_ACTIVE_LOW; + + /* PHY(RTL8211) requires 10ms pulse and 30ms release wait */ + t1 = 10000; + t2 = 30000; + } else + return; + + node = OF_finddevice("/soc/pinctrl"); + if (!node) + return; + + phandle = OF_getpropint(node, "phandle", 0); + if (!phandle) + return; + + gpio[0] = phandle; + gpio[1] = port; + gpio[2] = pin; + gpio[3] = flags; + gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT); + gpio_controller_set_pin(gpio, 1); + delay(t1); + gpio_controller_set_pin(gpio, 0); + delay(t2); +} + +void dwxe_attach(struct device *parent, struct device *self, void *aux) { struct dwxe_softc *sc = (void *)self; @@ -403,6 +453,9 @@ dwxe_attach(struct device *parent, struc phy_supply = OF_getpropint(faa->fa_node, "phy-supply", 0); if (phy_supply) regulator_enable(phy_supply); + + /* Reset PHY. */ + dwxe_reset_phy(); sc->sc_clk = clock_get_frequency(faa->fa_node, "stmmaceth"); if (sc->sc_clk > 160000000) Index: dev/ic/com.c =================================================================== RCS file: /cvs/src/sys/dev/ic/com.c,v retrieving revision 1.174 diff -u -p -u -p -r1.174 com.c --- dev/ic/com.c 6 May 2021 20:35:21 -0000 1.174 +++ dev/ic/com.c 4 Dec 2021 21:42:11 -0000 @@ -1300,7 +1300,7 @@ void com_attach_subr(struct com_softc *sc) { int probe = 0; - u_int8_t lcr; + u_int8_t lcr, fifo; sc->sc_ier = 0; /* disable interrupts */ @@ -1480,6 +1480,25 @@ com_attach_subr(struct com_softc *sc) SET(sc->sc_hwflags, COM_HW_FIFO); sc->sc_fifolen = 256; break; + case COM_UART_DW_APB: + printf(": DesignWare APB UART, "); + SET(sc->sc_hwflags, COM_HW_FIFO); + sc->sc_fifolen = CPR_FIFO_MODE(com_read_reg(sc, com_cpr)) * 16; + if (sc->sc_fifolen) { + printf("%d byte fifo\n", sc->sc_fifolen); + } else { + printf("no fifo\n"); + /* + * Allwinner H6's DW-APB configuration does not have + * CPR register and detect as no fifo. + * But this UART has 256 bytes FIFO and disabling FIFO + * makes problem; LSR_RXRDY is still set after + * reading com_data when FIFO is disabled (errata?). + * For workaround, treat as 1 byte FIFO. + */ + sc->sc_fifolen = 1; + } + break; default: panic("comattach: bad fifo type"); } @@ -1496,10 +1515,13 @@ com_attach_subr(struct com_softc *sc) } /* clear and disable fifo */ - com_write_reg(sc, com_fifo, FIFO_RCV_RST | FIFO_XMT_RST); + /* DW-APB UART cannot turn off FIFO here (ddb will not work) */ + fifo = (sc->sc_uarttype == COM_UART_DW_APB) ? + (FIFO_ENABLE | FIFO_TRIGGER_1) : 0; + com_write_reg(sc, com_fifo, fifo | FIFO_RCV_RST | FIFO_XMT_RST); if (ISSET(com_read_reg(sc, com_lsr), LSR_RXRDY)) (void)com_read_reg(sc, com_data); - com_write_reg(sc, com_fifo, 0); + com_write_reg(sc, com_fifo, fifo); sc->sc_mcr = 0; com_write_reg(sc, com_mcr, sc->sc_mcr); Index: dev/ic/comreg.h =================================================================== RCS file: /cvs/src/sys/dev/ic/comreg.h,v retrieving revision 1.20 diff -u -p -u -p -r1.20 comreg.h --- dev/ic/comreg.h 14 Aug 2020 18:14:11 -0000 1.20 +++ dev/ic/comreg.h 4 Dec 2021 21:42:11 -0000 @@ -180,6 +180,9 @@ #define ISR_TXPL 0x08 /* negative transmit data polarity */ #define ISR_RXPL 0x10 /* negative receive data polarity */ +/* component parameter register (Synopsys DesignWare APB UART) */ +#define CPR_FIFO_MODE(x) (((x) >> 16) & 0xff) + #define COM_NPORTS 8 /* Exar XR17V35X */ Index: dev/ic/comvar.h =================================================================== RCS file: /cvs/src/sys/dev/ic/comvar.h,v retrieving revision 1.58 diff -u -p -u -p -r1.58 comvar.h --- dev/ic/comvar.h 14 Aug 2020 18:14:11 -0000 1.58 +++ dev/ic/comvar.h 4 Dec 2021 21:42:11 -0000 @@ -104,6 +104,7 @@ struct com_softc { #define COM_UART_XR16850 0x10 /* 128 byte fifo */ #define COM_UART_OX16C950 0x11 /* 128 byte fifo */ #define COM_UART_XR17V35X 0x12 /* 256 byte fifo */ +#define COM_UART_DW_APB 0x13 /* configurable */ u_char sc_hwflags; #define COM_HW_NOIEN 0x01 Index: dev/ic/ns16550reg.h =================================================================== RCS file: /cvs/src/sys/dev/ic/ns16550reg.h,v retrieving revision 1.5 diff -u -p -u -p -r1.5 ns16550reg.h --- dev/ic/ns16550reg.h 2 Jun 2003 23:28:02 -0000 1.5 +++ dev/ic/ns16550reg.h 4 Dec 2021 21:42:11 -0000 @@ -50,3 +50,9 @@ #define com_lsr 5 /* line status register (R/W) */ #define com_msr 6 /* modem status register (R/W) */ #define com_scratch 7 /* scratch register (R/W) */ + +/* + * Synopsys DesignWare APB UART additional registers + */ +#define com_usr 31 /* UART status register (R) */ +#define com_cpr 61 /* component parameter register (R) */ Index: dev/ofw/ofw_regulator.c =================================================================== RCS file: /cvs/src/sys/dev/ofw/ofw_regulator.c,v retrieving revision 1.15 diff -u -p -u -p -r1.15 ofw_regulator.c --- dev/ofw/ofw_regulator.c 23 Dec 2020 11:58:36 -0000 1.15 +++ dev/ofw/ofw_regulator.c 4 Dec 2021 21:42:11 -0000 @@ -92,9 +92,25 @@ regulator_fixed_set(int node, int enable { uint32_t *gpio; uint32_t startup_delay; + uint32_t vin, vin_volt, vin_min, vin_max; int len; pinctrl_byname(node, "default"); + + /* turn on parent regulator (if exist) */ + vin = OF_getpropint(node, "vin-supply", 0); + if (vin) { + /* check voltage setting, fix if invalid */ + vin_volt = regulator_get_voltage(vin); + vin_min = OF_getpropint(vin, "regulator-min-microvolt", 0); + vin_max = OF_getpropint(vin, "regulator-max-microvolt", ~0); + if (vin_volt < vin_min) + regulator_set_voltage(vin, vin_min); + else if (vin_volt > vin_max) + regulator_set_voltage(vin, vin_max); + + regulator_enable(vin); + } /* The "gpio" property is optional. */ len = OF_getproplen(node, "gpio");