? arch/arm64/compile/GENERIC.MP/bsd.gdb
? arch/arm64/compile/GENERIC.MP/compile.sh
? arch/arm64/compile/GENERIC.MP/copy.sh
? arch/arm64/compile/RAMDISK/compile.sh
? arch/arm64/compile/RAMDISK/copy.sh
? arch/arm64/compile/RAMDISK/ramdisk
Index: dev/fdt/axppmic.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/axppmic.c,v
retrieving revision 1.16
diff -u -p -r1.16 axppmic.c
--- dev/fdt/axppmic.c	3 Sep 2022 18:05:10 -0000	1.16
+++ dev/fdt/axppmic.c	18 Dec 2022 03:21:16 -0000
@@ -306,6 +306,7 @@ const struct axppmic_device axppmic_devi
 	{ "x-powers,axp209", "AXP209", axp209_regdata, axp209_sensdata },
 	{ "x-powers,axp221", "AXP221", axp221_regdata, axp221_sensdata },
 	{ "x-powers,axp223", "AXP223", axp221_regdata, axp221_sensdata },
+	{ "x-powers,axp305", "AXP305", axp806_regdata },
 	{ "x-powers,axp803", "AXP803", axp803_regdata, axp803_sensdata },
 	{ "x-powers,axp805", "AXP805", axp806_regdata },
 	{ "x-powers,axp806", "AXP806", axp806_regdata },
@@ -511,7 +512,8 @@ axppmic_attach_common(struct axppmic_sof
 	sc->sc_sensdata = device->sensdata;
 
 	/* Switch AXP806 into master or slave mode. */
-	if (strcmp(name, "x-powers,axp805") == 0 ||
+	if (strcmp(name, "x-powers,axp305") == 0 ||
+	    strcmp(name, "x-powers,axp805") == 0 ||
 	    strcmp(name, "x-powers,axp806") == 0) {
 	    if (OF_getproplen(node, "x-powers,master-mode") == 0 ||
 	        OF_getproplen(node, "x-powers,self-working-mode") == 0) {
Index: dev/fdt/ehci_fdt.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/ehci_fdt.c,v
retrieving revision 1.9
diff -u -p -r1.9 ehci_fdt.c
--- dev/fdt/ehci_fdt.c	23 May 2022 11:37:22 -0000	1.9
+++ dev/fdt/ehci_fdt.c	18 Dec 2022 03:21:16 -0000
@@ -205,6 +205,7 @@ struct ehci_phy ehci_phys[] = {
 	{ "allwinner,sun8i-r40-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun8i-v3s-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun50i-h6-usb-phy", sun4i_phy_init },
+	{ "allwinner,sun50i-h616-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun50i-a64-usb-phy", sun4i_phy_init },
 	{ "allwinner,sun9i-a80-usb-phy", sun9i_phy_init },
 };
@@ -309,6 +310,13 @@ sun4i_phy_init(struct ehci_fdt_softc *sc
 	    OF_is_compatible(node, "allwinner,sun50i-a64-usb-phy")) {
 		val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
 		val &= ~(1 << 1);
+		bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
+	}
+	if (OF_is_compatible(node, "allwinner,sun50i-h616-usb-phy") ||
+	    OF_is_compatible(node, "allwinner,sun50i-a83t-usb-phy")) {
+		val = bus_space_read_4(sc->sc.iot, sc->sc.ioh, 0x810);
+		val |= 1 << 5;		/* set VBUSVLDEXT */
+		val &= ~(1 << 3);	/* clear SIDDQ */
 		bus_space_write_4(sc->sc.iot, sc->sc.ioh, 0x810, val);
 	}
 
Index: dev/fdt/if_dwxe.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/if_dwxe.c,v
retrieving revision 1.21
diff -u -p -r1.21 if_dwxe.c
--- dev/fdt/if_dwxe.c	9 Jul 2022 20:51:39 -0000	1.21
+++ dev/fdt/if_dwxe.c	18 Dec 2022 03:21:16 -0000
@@ -41,6 +41,7 @@
 
 #include <dev/ofw/openfirm.h>
 #include <dev/ofw/ofw_clock.h>
+#include <dev/ofw/ofw_gpio.h>
 #include <dev/ofw/ofw_misc.h>
 #include <dev/ofw/ofw_pinctrl.h>
 #include <dev/ofw/ofw_regulator.h>
@@ -351,6 +352,7 @@ void	dwxe_iff(struct dwxe_softc *);
 int	dwxe_encap(struct dwxe_softc *, struct mbuf *, int *, int *);
 
 void	dwxe_reset(struct dwxe_softc *);
+void	dwxe_reset_phy(void);
 void	dwxe_stop_dma(struct dwxe_softc *);
 
 struct dwxe_dmamem *
@@ -370,6 +372,54 @@ dwxe_match(struct device *parent, void *
 }
 
 void
+dwxe_reset_phy(void)
+{
+	int node, t1, t2;
+	uint32_t phandle, port, pin, flags;
+	uint32_t gpio[4];
+
+	node = OF_finddevice("/");
+	if (!node)
+		return;
+
+	/*
+	 * There is no binding definiton about the GPIO that is used for
+	 * resetting external PHY. But some boards have GPIO connected to 
+	 * PHY's reset and need to assert at dwxe_attach().
+	 * This is workaround.
+	 */
+	if (OF_is_compatible(node, "xunlong,orangepi-one-plus")) {
+		/* PD14, active-low */
+		port = 3;
+		pin = 14;
+		flags = GPIO_ACTIVE_LOW;
+
+		/* PHY(RTL8211) requires 10ms pulse and 30ms release wait */
+		t1 = 10000;
+		t2 = 30000;
+	} else
+		return;
+
+	node = OF_finddevice("/soc/pinctrl");
+	if (!node)
+		return;
+
+	phandle = OF_getpropint(node, "phandle", 0);
+	if (!phandle)
+		return;		
+
+	gpio[0] = phandle;
+	gpio[1] = port;
+	gpio[2] = pin;
+	gpio[3] = flags;
+	gpio_controller_config_pin(gpio, GPIO_CONFIG_OUTPUT);
+	gpio_controller_set_pin(gpio, 1);
+	delay(t1);
+	gpio_controller_set_pin(gpio, 0);
+	delay(t2);
+}
+
+void
 dwxe_attach(struct device *parent, struct device *self, void *aux)
 {
 	struct dwxe_softc *sc = (void *)self;
@@ -394,6 +444,9 @@ dwxe_attach(struct device *parent, struc
 		sc->sc_phyloc = OF_getpropint(node, "reg", MII_PHY_ANY);
 	else
 		sc->sc_phyloc = MII_PHY_ANY;
+
+	/* Reset PHY. */
+	dwxe_reset_phy();
 
 	sc->sc_clk = clock_get_frequency(faa->fa_node, "stmmaceth");
 	if (sc->sc_clk > 160000000)
Index: dev/fdt/sxiccmu.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu.c,v
retrieving revision 1.31
diff -u -p -r1.31 sxiccmu.c
--- dev/fdt/sxiccmu.c	28 Jun 2022 23:43:12 -0000	1.31
+++ dev/fdt/sxiccmu.c	18 Dec 2022 03:21:17 -0000
@@ -104,6 +104,9 @@ uint32_t sxiccmu_h3_r_get_frequency(stru
 uint32_t sxiccmu_h6_get_frequency(struct sxiccmu_softc *, uint32_t);
 int	sxiccmu_h6_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 uint32_t sxiccmu_h6_r_get_frequency(struct sxiccmu_softc *, uint32_t);
+uint32_t sxiccmu_h616_get_frequency(struct sxiccmu_softc *, uint32_t);
+int	sxiccmu_h616_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
+uint32_t sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *, uint32_t);
 uint32_t sxiccmu_r40_get_frequency(struct sxiccmu_softc *, uint32_t);
 int	sxiccmu_r40_set_frequency(struct sxiccmu_softc *, uint32_t, uint32_t);
 uint32_t sxiccmu_v3s_get_frequency(struct sxiccmu_softc *, uint32_t);
@@ -149,7 +152,9 @@ sxiccmu_match(struct device *parent, voi
 	    OF_is_compatible(node, "allwinner,sun50i-a64-r-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-h5-ccu") ||
 	    OF_is_compatible(node, "allwinner,sun50i-h6-ccu") ||
-	    OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu"));
+	    OF_is_compatible(node, "allwinner,sun50i-h6-r-ccu") ||
+	    OF_is_compatible(node, "allwinner,sun50i-h616-ccu") ||
+	    OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu"));
 }
 
 void
@@ -276,6 +281,22 @@ sxiccmu_attach(struct device *parent, st
 		sc->sc_nresets = nitems(sun50i_h6_r_resets);
 		sc->sc_get_frequency = sxiccmu_h6_r_get_frequency;
 		sc->sc_set_frequency = sxiccmu_nop_set_frequency;
+	} else if (OF_is_compatible(node, "allwinner,sun50i-h616-ccu")) {
+		KASSERT(faa->fa_nreg > 0);
+		sc->sc_gates = sun50i_h616_gates;
+		sc->sc_ngates = nitems(sun50i_h616_gates);
+		sc->sc_resets = sun50i_h616_resets;
+		sc->sc_nresets = nitems(sun50i_h616_resets);
+		sc->sc_get_frequency = sxiccmu_h616_get_frequency;
+		sc->sc_set_frequency = sxiccmu_h616_set_frequency;
+	} else if (OF_is_compatible(node, "allwinner,sun50i-h616-r-ccu")) {
+		KASSERT(faa->fa_nreg > 0);
+		sc->sc_gates = sun50i_h616_r_gates;
+		sc->sc_ngates = nitems(sun50i_h616_r_gates);
+		sc->sc_resets = sun50i_h616_r_resets;
+		sc->sc_nresets = nitems(sun50i_h616_r_resets);
+		sc->sc_get_frequency = sxiccmu_h616_r_get_frequency;
+		sc->sc_set_frequency = sxiccmu_nop_set_frequency;
 	} else {
 		for (node = OF_child(node); node; node = OF_peer(node))
 			sxiccmu_attach_clock(sc, node, faa->fa_nreg);
@@ -1338,7 +1359,6 @@ sxiccmu_h6_get_frequency(struct sxiccmu_
 	case H6_CLK_APB2:
 		/* XXX Controlled by a MUX. */
 		return 24000000;
-		break;
 	}
 
 	printf("%s: 0x%08x\n", __func__, idx);
@@ -1352,7 +1372,52 @@ sxiccmu_h6_r_get_frequency(struct sxiccm
 	case H6_R_CLK_APB2:
 		/* XXX Controlled by a MUX. */
 		return 24000000;
-		break;
+	}
+
+	printf("%s: 0x%08x\n", __func__, idx);
+	return 0;
+}
+
+/* Allwinner H616 */
+#define H616_AHB3_CFG_REG		0x051c
+#define H616_AHB3_CLK_FACTOR_N(x)	(((x) >> 8) & 0x3)
+#define H616_AHB3_CLK_FACTOR_M(x)	(((x) >> 0) & 0x3)
+
+uint32_t
+sxiccmu_h616_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+	uint32_t reg, m, n;
+	uint32_t freq;
+
+	switch (idx) {
+	case H616_CLK_PLL_PERIPH0:
+		/* Not hardcoded, but recommended. */
+		return 600000000;
+	case H616_CLK_PLL_PERIPH0_2X:
+		return sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0) * 2;
+	case H616_CLK_AHB3:
+		reg = SXIREAD4(sc, H616_AHB3_CFG_REG);
+		/* assume PLL_PERIPH0 source */
+		freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0);
+		m = H616_AHB3_CLK_FACTOR_M(reg) + 1;
+		n = 1 << H616_AHB3_CLK_FACTOR_N(reg);
+		return freq / (m * n);
+	case H616_CLK_APB2:
+		/* XXX Controlled by a MUX. */
+		return 24000000;
+	}
+
+	printf("%s: 0x%08x\n", __func__, idx);
+	return 0;
+}
+
+uint32_t
+sxiccmu_h616_r_get_frequency(struct sxiccmu_softc *sc, uint32_t idx)
+{
+	switch (idx) {
+	case H616_R_CLK_APB2:
+		/* XXX Controlled by a MUX. */
+		return 24000000;
 	}
 
 	printf("%s: 0x%08x\n", __func__, idx);
@@ -1732,9 +1797,8 @@ sxiccmu_h3_set_frequency(struct sxiccmu_
 
 int
 sxiccmu_h6_mmc_set_frequency(struct sxiccmu_softc *sc, bus_size_t offset,
-    uint32_t freq)
+    uint32_t freq, uint32_t parent_freq)
 {
-	uint32_t parent_freq;
 	uint32_t reg, m, n;
 	uint32_t clk_src;
 
@@ -1750,8 +1814,6 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
 	case 52000000:
 		n = 0, m = 0;
 		clk_src = H6_SMHC_CLK_SRC_SEL_PLL_PERIPH0_2X;
-		parent_freq =
-		    sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
 		while ((parent_freq / (1 << n) / 16) > freq)
 			n++;
 		while ((parent_freq / (1 << n) / (m + 1)) > freq)
@@ -1776,13 +1838,47 @@ sxiccmu_h6_mmc_set_frequency(struct sxic
 int
 sxiccmu_h6_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
 {
+	uint32_t parent_freq;
+
+	parent_freq = sxiccmu_h6_get_frequency(sc, H6_CLK_PLL_PERIPH0_2X);
+
 	switch (idx) {
 	case H6_CLK_MMC0:
-		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG, freq);
+		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC0_CLK_REG,
+						    freq, parent_freq);
 	case H6_CLK_MMC1:
-		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG, freq);
+		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC1_CLK_REG,
+						    freq, parent_freq);
 	case H6_CLK_MMC2:
-		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG, freq);
+		return sxiccmu_h6_mmc_set_frequency(sc, H6_SMHC2_CLK_REG,
+						    freq, parent_freq);
+	}
+
+	printf("%s: 0x%08x\n", __func__, idx);
+	return -1;
+}
+
+#define H616_SMHC0_CLK_REG		0x0830
+#define H616_SMHC1_CLK_REG		0x0834
+#define H616_SMHC2_CLK_REG		0x0838
+
+int
+sxiccmu_h616_set_frequency(struct sxiccmu_softc *sc, uint32_t idx, uint32_t freq)
+{
+	uint32_t parent_freq;
+
+	parent_freq = sxiccmu_h616_get_frequency(sc, H616_CLK_PLL_PERIPH0_2X);
+
+	switch (idx) {
+	case H616_CLK_MMC0:
+		return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC0_CLK_REG,
+						    freq, parent_freq);
+	case H616_CLK_MMC1:
+		return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC1_CLK_REG,
+						    freq, parent_freq);
+	case H616_CLK_MMC2:
+		return sxiccmu_h6_mmc_set_frequency(sc, H616_SMHC2_CLK_REG,
+						    freq, parent_freq);
 	}
 
 	printf("%s: 0x%08x\n", __func__, idx);
Index: dev/fdt/sxiccmu_clocks.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxiccmu_clocks.h,v
retrieving revision 1.33
diff -u -p -r1.33 sxiccmu_clocks.h
--- dev/fdt/sxiccmu_clocks.h	28 Jun 2022 23:43:12 -0000	1.33
+++ dev/fdt/sxiccmu_clocks.h	18 Dec 2022 03:21:17 -0000
@@ -468,6 +468,100 @@ const struct sxiccmu_ccu_bit sun50i_h6_r
 	[H6_R_CLK_APB2_RSB] = { 0x01bc, 0, H6_R_CLK_APB2 },
 };
 
+/* H616 */
+
+#define H616_CLK_PLL_PERIPH0	4
+#define H616_CLK_PLL_PERIPH0_2X	5
+#define H616_CLK_AHB3		25
+#define H616_CLK_APB1		26
+#define H616_CLK_APB2		27
+#define H616_CLK_MMC0		60
+#define H616_CLK_MMC1		61
+#define H616_CLK_MMC2		62
+#define H616_CLK_BUS_MMC0	63
+#define H616_CLK_BUS_MMC1	64
+#define H616_CLK_BUS_MMC2	65
+#define H616_CLK_BUS_UART0	66
+#define H616_CLK_BUS_UART1	67
+#define H616_CLK_BUS_UART2	68
+#define H616_CLK_BUS_UART3	69
+#define H616_CLK_BUS_UART4	70
+#define H616_CLK_BUS_UART5	71
+#define H616_CLK_BUS_I2C0	72
+#define H616_CLK_BUS_I2C1	73
+#define H616_CLK_BUS_I2C2	74
+#define H616_CLK_BUS_I2C3	75
+#define H616_CLK_BUS_I2C4	76
+#define H616_CLK_BUS_EMAC0	82
+#define H616_CLK_BUS_EMAC1	83
+#define H616_CLK_USB_OHCI0	96
+#define H616_CLK_USB_PHY0	97
+#define H616_CLK_USB_OHCI1	98
+#define H616_CLK_USB_PHY1	99
+#define H616_CLK_USB_OHCI2	100
+#define H616_CLK_USB_PHY2	101
+#define H616_CLK_USB_OHCI3	102
+#define H616_CLK_USB_PHY3	103
+#define H616_CLK_BUS_OHCI0	104
+#define H616_CLK_BUS_OHCI1	105
+#define H616_CLK_BUS_OHCI2	106
+#define H616_CLK_BUS_OHCI3	107
+#define H616_CLK_BUS_EHCI0	108
+#define H616_CLK_BUS_EHCI1	109
+#define H616_CLK_BUS_EHCI2	110
+#define H616_CLK_BUS_EHCI3	111
+
+struct sxiccmu_ccu_bit sun50i_h616_gates[] = {
+	[H616_CLK_PLL_PERIPH0] = { 0x0020, 31 },
+	[H616_CLK_APB1] = { 0xffff, 0xff },
+	[H616_CLK_MMC0] = { 0x0830, 31 },
+	[H616_CLK_MMC1] = { 0x0834, 31 },
+	[H616_CLK_MMC2] = { 0x0838, 31 },
+	[H616_CLK_BUS_MMC0] = { 0x084c, 0 },
+	[H616_CLK_BUS_MMC1] = { 0x084c, 1 },
+	[H616_CLK_BUS_MMC2] = { 0x084c, 2 },
+	[H616_CLK_BUS_UART0] = { 0x090c, 0, H616_CLK_APB2 },
+	[H616_CLK_BUS_UART1] = { 0x090c, 1, H616_CLK_APB2 },
+	[H616_CLK_BUS_UART2] = { 0x090c, 2, H616_CLK_APB2 },
+	[H616_CLK_BUS_UART3] = { 0x090c, 3, H616_CLK_APB2 },
+	[H616_CLK_BUS_UART4] = { 0x090c, 4, H616_CLK_APB2 },
+	[H616_CLK_BUS_UART5] = { 0x090c, 5, H616_CLK_APB2 },
+	[H616_CLK_BUS_I2C0] = { 0x091c, 0, H616_CLK_APB2 },
+	[H616_CLK_BUS_I2C1] = { 0x091c, 1, H616_CLK_APB2 },
+	[H616_CLK_BUS_I2C2] = { 0x091c, 2, H616_CLK_APB2 },
+	[H616_CLK_BUS_I2C3] = { 0x091c, 3, H616_CLK_APB2 },
+	[H616_CLK_BUS_I2C4] = { 0x091c, 4, H616_CLK_APB2 },
+	[H616_CLK_BUS_EMAC0] = { 0x097c, 0, H616_CLK_AHB3 },
+	[H616_CLK_BUS_EMAC1] = { 0x097c, 1, H616_CLK_AHB3 },
+	[H616_CLK_USB_OHCI0] = { 0x0a70, 31 },
+	[H616_CLK_USB_PHY0] = { 0x0a70, 29 },
+	[H616_CLK_USB_OHCI1] = { 0x0a74, 31 },
+	[H616_CLK_USB_PHY1] = { 0x0a74, 29 },
+	[H616_CLK_USB_OHCI2] = { 0x0a78, 31 },
+	[H616_CLK_USB_PHY2] = { 0x0a78, 29 },
+	[H616_CLK_USB_OHCI3] = { 0x0a7c, 31 },
+	[H616_CLK_USB_PHY3] = { 0x0a7c, 29 },
+	[H616_CLK_BUS_OHCI0] = { 0x0a8c, 0 },
+	[H616_CLK_BUS_OHCI1] = { 0x0a8c, 1 },
+	[H616_CLK_BUS_OHCI2] = { 0x0a8c, 2 },
+	[H616_CLK_BUS_OHCI3] = { 0x0a8c, 3 },
+	[H616_CLK_BUS_EHCI0] = { 0x0a8c, 4 },
+	[H616_CLK_BUS_EHCI1] = { 0x0a8c, 5 },
+	[H616_CLK_BUS_EHCI2] = { 0x0a8c, 6 },
+	[H616_CLK_BUS_EHCI3] = { 0x0a8c, 7 },
+};
+
+#define H616_R_CLK_APB1		2
+#define H616_R_CLK_APB2		3
+#define H616_R_CLK_APB2_I2C	8
+#define H616_R_CLK_APB2_RSB	13
+
+struct sxiccmu_ccu_bit sun50i_h616_r_gates[] = {
+	[H616_R_CLK_APB1] = { 0xffff, 0xff },
+	[H616_R_CLK_APB2_I2C] = { 0x019c, 0, H616_R_CLK_APB2 },
+	[H616_R_CLK_APB2_RSB] = { 0x01bc, 0, H616_R_CLK_APB2 },
+};
+
 /* R40 */
 
 #define R40_CLK_PLL_PERIPH0	11
@@ -877,6 +971,76 @@ const struct sxiccmu_ccu_bit sun50i_h6_r
 const struct sxiccmu_ccu_bit sun50i_h6_r_resets[] = {
 	[H6_R_RST_APB2_I2C] = { 0x019c, 16 },
 	[H6_R_RST_APB2_RSB] = { 0x01bc, 16 },
+};
+
+/* H616 */
+
+#define H616_RST_BUS_MMC0	14
+#define H616_RST_BUS_MMC1	15
+#define H616_RST_BUS_MMC2	16
+#define H616_RST_BUS_UART0	17
+#define H616_RST_BUS_UART1	18
+#define H616_RST_BUS_UART2	19
+#define H616_RST_BUS_UART3	20
+#define H616_RST_BUS_UART4	21
+#define H616_RST_BUS_UART5	22
+#define H616_RST_BUS_I2C0	23
+#define H616_RST_BUS_I2C1	24
+#define H616_RST_BUS_I2C2	25
+#define H616_RST_BUS_I2C3	26
+#define H616_RST_BUS_I2C4	27
+#define H616_RST_BUS_EMAC0	30
+#define H616_RST_BUS_EMAC1	31
+#define H616_RST_USB_PHY0	38
+#define H616_RST_USB_PHY1	39
+#define H616_RST_USB_PHY2	40
+#define H616_RST_USB_PHY3	41
+#define H616_RST_BUS_OHCI0	42
+#define H616_RST_BUS_OHCI1	43
+#define H616_RST_BUS_OHCI2	44
+#define H616_RST_BUS_OHCI3	45
+#define H616_RST_BUS_EHCI0	46
+#define H616_RST_BUS_EHCI1	47
+#define H616_RST_BUS_EHCI2	48
+#define H616_RST_BUS_EHCI3	49
+
+struct sxiccmu_ccu_bit sun50i_h616_resets[] = {
+	[H616_RST_BUS_MMC0] = { 0x084c, 16 },
+	[H616_RST_BUS_MMC1] = { 0x084c, 17 },
+	[H616_RST_BUS_MMC2] = { 0x084c, 18 },
+	[H616_RST_BUS_UART0] = { 0x090c, 16 },
+	[H616_RST_BUS_UART1] = { 0x090c, 17 },
+	[H616_RST_BUS_UART2] = { 0x090c, 18 },
+	[H616_RST_BUS_UART3] = { 0x090c, 19 },
+	[H616_RST_BUS_UART4] = { 0x090c, 20 },
+	[H616_RST_BUS_UART5] = { 0x090c, 21 },
+	[H616_RST_BUS_I2C0] = { 0x091c, 16 },
+	[H616_RST_BUS_I2C1] = { 0x091c, 17 },
+	[H616_RST_BUS_I2C2] = { 0x091c, 18 },
+	[H616_RST_BUS_I2C3] = { 0x091c, 19 },
+	[H616_RST_BUS_I2C4] = { 0x091c, 20 },
+	[H616_RST_BUS_EMAC0] = { 0x097c, 16 },
+	[H616_RST_BUS_EMAC1] = { 0x097c, 17 },
+	[H616_RST_USB_PHY0] = { 0x0a70, 30 },
+	[H616_RST_USB_PHY1] = { 0x0a74, 30 },
+	[H616_RST_USB_PHY2] = { 0x0a78, 30 },
+	[H616_RST_USB_PHY3] = { 0x0a7c, 30 },
+	[H616_RST_BUS_OHCI0] = { 0x0a8c, 16 },
+	[H616_RST_BUS_OHCI1] = { 0x0a8c, 17 },
+	[H616_RST_BUS_OHCI2] = { 0x0a8c, 18 },
+	[H616_RST_BUS_OHCI3] = { 0x0a8c, 19 },
+	[H616_RST_BUS_EHCI0] = { 0x0a8c, 20 },
+	[H616_RST_BUS_EHCI1] = { 0x0a8c, 21 },
+	[H616_RST_BUS_EHCI2] = { 0x0a8c, 22 },
+	[H616_RST_BUS_EHCI3] = { 0x0a8c, 23 },
+};
+
+#define H616_R_RST_APB2_I2C	4
+#define H616_R_RST_APB2_RSB	7
+
+struct sxiccmu_ccu_bit sun50i_h616_r_resets[] = {
+	[H616_R_RST_APB2_I2C] = { 0x019c, 16 },
+	[H616_R_RST_APB2_RSB] = { 0x01bc, 16 },
 };
 
 /* R40 */
Index: dev/fdt/sximmc.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sximmc.c,v
retrieving revision 1.12
diff -u -p -r1.12 sximmc.c
--- dev/fdt/sximmc.c	24 Oct 2021 17:52:27 -0000	1.12
+++ dev/fdt/sximmc.c	18 Dec 2022 03:21:17 -0000
@@ -205,6 +205,9 @@ struct sximmc_idma_descriptor {
 #define SXIMMC_DMA_FTRGLEVEL_A20	0x20070008
 #define SXIMMC_DMA_FTRGLEVEL_A80	0x200f0010
 
+#define SXIMMC_IDMA_ADDRSHIFT_NONE	0
+#define SXIMMC_IDMA_ADDRSHIFT_A100	2
+
 int	sximmc_match(struct device *, void *, void *);
 void	sximmc_attach(struct device *, struct device *, void *);
 
@@ -265,6 +268,7 @@ struct sximmc_softc {
 	uint32_t sc_intr_rint;
 	uint32_t sc_intr_mint;
 	uint32_t sc_idma_idst;
+	uint32_t sc_idma_addrshift;
 
 	uint32_t sc_gpio[4];
 	uint32_t sc_vmmc;
@@ -298,7 +302,9 @@ sximmc_match(struct device *parent, void
 	    OF_is_compatible(faa->fa_node, "allwinner,sun7i-a20-mmc") ||
 	    OF_is_compatible(faa->fa_node, "allwinner,sun9i-a80-mmc") ||
 	    OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-mmc") ||
-	    OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc"));
+	    OF_is_compatible(faa->fa_node, "allwinner,sun50i-a64-emmc") ||
+	    OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-mmc") ||
+	    OF_is_compatible(faa->fa_node, "allwinner,sun50i-a100-emmc"));
 }
 
 int
@@ -394,6 +400,11 @@ sximmc_attach(struct device *parent, str
 	else
 		sc->sc_dma_ftrglevel = SXIMMC_DMA_FTRGLEVEL_A20;
 
+	if (OF_is_compatible(sc->sc_node, "allwinner,sun50i-a100-mmc"))
+		sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_A100;
+	else
+		sc->sc_idma_addrshift = SXIMMC_IDMA_ADDRSHIFT_NONE;
+
 	if (sc->sc_use_dma) {
 		if (sximmc_idma_setup(sc) != 0) {
 			printf("%s: failed to setup DMA\n", self->dv_xname);
@@ -854,7 +865,7 @@ sximmc_dma_prepare(struct sximmc_softc *
 		bus_addr_t paddr = cmd->c_dmamap->dm_segs[seg].ds_addr;
 		bus_size_t len = cmd->c_dmamap->dm_segs[seg].ds_len;
 		dma[seg].dma_buf_size = htole32(len);
-		dma[seg].dma_buf_addr = htole32(paddr);
+		dma[seg].dma_buf_addr = htole32(paddr >> sc->sc_idma_addrshift);
 		dma[seg].dma_config = htole32(SXIMMC_IDMA_CONFIG_CH |
 		    SXIMMC_IDMA_CONFIG_OWN);
 		if (seg == 0) {
@@ -871,8 +882,9 @@ sximmc_dma_prepare(struct sximmc_softc *
 			dma[seg].dma_config |=
 			    htole32(SXIMMC_IDMA_CONFIG_DIC);
 			dma[seg].dma_next = htole32(
-			    desc_paddr + ((seg + 1) *
-			    sizeof(struct sximmc_idma_descriptor)));
+			    (desc_paddr + ((seg + 1) *
+			     sizeof(struct sximmc_idma_descriptor))) >>
+			    sc->sc_idma_addrshift);
 		}
 	}
 
@@ -897,7 +909,7 @@ sximmc_dma_prepare(struct sximmc_softc *
 	else
 		val |= SXIMMC_IDST_TRANSMIT_INT;
 	MMC_WRITE(sc, SXIMMC_IDIE, val);
-	MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr);
+	MMC_WRITE(sc, SXIMMC_DLBA, desc_paddr >> sc->sc_idma_addrshift);
 	MMC_WRITE(sc, SXIMMC_FTRGLEVEL, sc->sc_dma_ftrglevel);
 
 	return 0;
Index: dev/fdt/sxipio.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio.c,v
retrieving revision 1.15
diff -u -p -r1.15 sxipio.c
--- dev/fdt/sxipio.c	28 Jun 2022 23:43:12 -0000	1.15
+++ dev/fdt/sxipio.c	18 Dec 2022 03:21:17 -0000
@@ -198,6 +198,14 @@ const struct sxipio_pins sxipio_pins[] =
 		"allwinner,sun50i-h6-r-pinctrl",
 		sun50i_h6_r_pins, nitems(sun50i_h6_r_pins)
 	},
+	{
+		"allwinner,sun50i-h616-pinctrl",
+		sun50i_h616_pins, nitems(sun50i_h616_pins)
+	},
+	{
+		"allwinner,sun50i-h616-r-pinctrl",
+		sun50i_h616_r_pins, nitems(sun50i_h616_r_pins)
+	},
 };
 
 int
Index: dev/fdt/sxipio_pins.h
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxipio_pins.h,v
retrieving revision 1.8
diff -u -p -r1.8 sxipio_pins.h
--- dev/fdt/sxipio_pins.h	28 Jun 2022 23:43:12 -0000	1.8
+++ dev/fdt/sxipio_pins.h	18 Dec 2022 03:21:17 -0000
@@ -9858,3 +9858,600 @@ const struct sxipio_pin sun50i_h6_r_pins
 		{ "irq", 6 },
 	} },
 };
+
+struct sxipio_pin sun50i_h616_pins[] = {
+	{ SXIPIO_PIN(A, 0), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 1), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 2), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 3), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 4), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 5), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 6), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 7), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 8), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 9), {
+		{ "emac1", 2 },
+	} },
+	{ SXIPIO_PIN(A, 10), {
+		{ "i2c3", 2 },
+	} },
+	{ SXIPIO_PIN(A, 11), {
+		{ "i2c3", 2 },
+	} },
+	{ SXIPIO_PIN(A, 12), {
+		{ "pwm5", 2 },
+	} },
+	{ SXIPIO_PIN(C, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 2), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 3), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 4), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 5), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 6), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 7), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 8), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 9), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 10), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 11), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 12), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 13), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 14), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 15), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(C, 16), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "nand0", 2 },
+		{ "mmc2", 3 },
+		{ "spi0", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "jtag", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "jtag", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 2), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "uart0", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 3), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "jtag", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 4), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "uart0", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 5), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc0", 2 },
+		{ "jtag", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(F, 6), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 2), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 3), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 4), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 5), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "mmc1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 6), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart1", 2 },
+		{ "jtag", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 7), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart1", 2 },
+		{ "jtag", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 8), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart1", 2 },
+		{ "clock", 3 },
+		{ "jtag", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 9), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart1", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 10), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s2", 2 },
+		{ "clock", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 11), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s2", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 12), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s2", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 13), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s2", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 14), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s2", 2 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 15), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2c4", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 16), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2c4", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 17), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2c3", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 18), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2c3", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(G, 19), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "pwm1", 4 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart0", 2 },
+		{ "pwm3", 4 },
+		{ "i2c1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart0", 2 },
+		{ "pwm4", 4 },
+		{ "i2c1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 2), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart5", 2 },
+		{ "spdif", 3 },
+		{ "pwm2", 4 },
+		{ "i2c2", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 3), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart5", 2 },
+		{ "pwm1", 4 },
+		{ "i2c2", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 4), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "spdif", 3 },
+		{ "i2c3", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 5), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2s3", 3 },
+		{ "spi1", 4 },
+		{ "i2c3", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 6), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2s3", 3 },
+		{ "spi1", 4 },
+		{ "i2c4", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 7), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2s3", 3 },
+		{ "spi1", 4 },
+		{ "i2c4", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 8), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "uart2", 2 },
+		{ "i2s3_dout0", 3 },
+		{ "spi1", 4 },
+		{ "i2s3_din1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 9), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "i2s3_din0", 3 },
+		{ "spi1", 4 },
+		{ "i2s3_dout1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(H, 10), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "ir_rx", 3 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "dmic", 3 },
+		{ "i2s0", 4 },
+		{ "hdmi", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "dmic", 3 },
+		{ "i2s0", 4 },
+		{ "hdmi", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 2), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "dmic", 3 },
+		{ "i2s0", 4 },
+		{ "hdmi", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 3), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "dmic", 3 },
+		{ "i2s0_dout0", 4 },
+		{ "i2s0_din1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 4), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "dmic", 3 },
+		{ "i2s0_din0", 4 },
+		{ "i2s0_dout1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 5), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart2", 3 },
+		{ "ts0", 4 },
+		{ "i2c0", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 6), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart2", 3 },
+		{ "ts0", 4 },
+		{ "i2c0", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 7), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart2", 3 },
+		{ "ts0", 4 },
+		{ "i2c1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 8), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart2", 3 },
+		{ "ts0", 4 },
+		{ "i2c1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 9), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart3", 3 },
+		{ "ts0", 4 },
+		{ "i2c2", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 10), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart3", 3 },
+		{ "ts0", 4 },
+		{ "i2c2", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 11), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart3", 3 },
+		{ "ts0", 4 },
+		{ "pwm1", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 12), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart3", 3 },
+		{ "ts0", 4 },
+		{ "pwm2", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 13), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart4", 3 },
+		{ "ts0", 4 },
+		{ "pwm3", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 14), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart4", 3 },
+		{ "ts0", 4 },
+		{ "pwm4", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 15), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart4", 3 },
+		{ "ts0", 4 },
+		{ "clock", 5 },
+		{ "irq", 6 },
+	} },
+	{ SXIPIO_PIN(I, 16), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "emac0", 2 },
+		{ "uart4", 3 },
+		{ "ts0", 4 },
+		{ "clock", 5 },
+		{ "irq", 6 },
+	} },
+};
+
+struct sxipio_pin sun50i_h616_r_pins[] = {
+	{ SXIPIO_PIN(L, 0), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "s_rsb", 2 },
+		{ "s_i2c", 3 },
+	} },
+	{ SXIPIO_PIN(L, 1), {
+		{ "gpio_in", 0 },
+		{ "gpio_out", 1 },
+		{ "s_rsb", 2 },
+		{ "s_i2c", 3 },
+	} },
+};
Index: dev/fdt/sxisyscon.c
===================================================================
RCS file: /cvs/src/sys/dev/fdt/sxisyscon.c,v
retrieving revision 1.2
diff -u -p -r1.2 sxisyscon.c
--- dev/fdt/sxisyscon.c	24 Oct 2021 17:52:27 -0000	1.2
+++ dev/fdt/sxisyscon.c	18 Dec 2022 03:21:17 -0000
@@ -52,7 +52,8 @@ sxisyscon_match(struct device *parent, v
 	if (OF_is_compatible(node, "allwinner,sun8i-h3-system-control") ||
 	    OF_is_compatible(node, "allwinner,sun50i-a64-system-control") ||
 	    OF_is_compatible(node, "allwinner,sun50i-h5-system-control") ||
-	    OF_is_compatible(node, "allwinner,sun50i-h6-system-control"))
+	    OF_is_compatible(node, "allwinner,sun50i-h6-system-control") ||
+	    OF_is_compatible(node, "allwinner,sun50i-h616-system-control"))
 		return 10;	/* Must beat syscon(4). */
 
 	return 0;
Index: dev/ofw/ofw_regulator.c
===================================================================
RCS file: /cvs/src/sys/dev/ofw/ofw_regulator.c,v
retrieving revision 1.16
diff -u -p -r1.16 ofw_regulator.c
--- dev/ofw/ofw_regulator.c	14 Feb 2022 12:54:43 -0000	1.16
+++ dev/ofw/ofw_regulator.c	18 Dec 2022 03:21:17 -0000
@@ -92,9 +92,25 @@ regulator_fixed_set(int node, int enable
 {
 	uint32_t *gpio;
 	uint32_t startup_delay;
+	uint32_t vin, vin_volt, vin_min, vin_max;
 	int len;
 
 	pinctrl_byname(node, "default");
+
+	/* turn on parent regulator (if exist) */
+	vin = OF_getpropint(node, "vin-supply", 0);
+	if (vin) {
+		/* check voltage setting, fix if invalid */
+		vin_volt = regulator_get_voltage(vin);
+		vin_min = OF_getpropint(vin, "regulator-min-microvolt", 0);
+		vin_max = OF_getpropint(vin, "regulator-max-microvolt", ~0);
+		if (vin_volt < vin_min)
+			regulator_set_voltage(vin, vin_min);
+		else if (vin_volt > vin_max)
+			regulator_set_voltage(vin, vin_max);
+
+		regulator_enable(vin);
+	}
 
 	/* The "gpio" property is optional. */
 	len = OF_getproplen(node, "gpio");